1. Field of the Invention
The present invention relates to a sample-and-hold circuit.
2. Description of the Related Art
An example of a known sample-and-hold circuit is shown in FIG. 5. This circuit is used for an active-matrix liquid crystal display device, for example. As shown, an analog signal such as a video signal to be sampled and held is entered from an input signal line 25. Elements 13 and 17 are capacitors (including stray capacitance of the circuit), which serve to hold the voltge of the analog signal Y. Each one end of the capacitors is connected to the ground. The other ends of the capacitors are connected so that the analog signal Y can enter the capacitors through analog switches 12, 16, respectively. The voltages held in the capacitors 13, 17 are inputted to a non-inverting input of an operational amplifier 19 through analog switches 14, 18, respectively. A capacitor 15 and an analog switch constituted by an MOS transistor 21 are connected between the non-inverting input terminal of the operational amplifier 19 and the ground. Element 22 is a MOS transistor connected between an output of a buffer 20 and the ground. A control signal R is inputted to the gates of the transistors 21, 22 through a signal line 10.
The operational amplifier 19 is composed of a differential amplifier as shown in FIG. 6. Herein, N41 and N42 each denote an n-channel MOS transistor. The MOS transistor N41 has a gate connected to the non-inverting input of the operational amplifier 19 and the MOS transistor N42 has a gate connected to the inverting input of the operational amplifier 19. The transistor N41 is connected between an n-channel MOS transistor N43 connected to the ground and a p-channel MOS transistor P41 connected to a power supply VDD. The transistor N42 is connected between the transistor N43 and a p-channel MOS transistor P42 connected to the power supply VDD. A contact between the transistors N42 and P42 serves as an output of this operational amplifier.
When the input signal Y is sampled and held at predetermined periods, the sample-and-hold circuit arranged as described above receives control signals R and S1 to S4 as shown in the timing chart of FIG. 7. In response to the control signals, the circuit functions as follows. When a high level control signal S1 is inputted to the circuit at a timing point T1, the analog switch 12 is switched on so that the signal Y is applied to the capacitor 13. Hence, the capacitor 13 is charged. Then, the signal S1 falls to the low level and the analog switch 12 is switched off, and the capacitor 13 holds the voltage D1 of the signal Y immediately before the fall. Next, the high level control signal R is supplied to the circuit, whereby the transistors 21, 22 turn on so that the output of the buffer 20 falls to the ground level. Hence, the capacitor 15 is discharged. When the control signal S3 rises to the high level, the analog switch 14 is switched on, so that the charges of the capacitor 13 are moved to the capacitor 15. As a result, the voltage at the terminals of the capacitors 13 and 15 is made to be a value D1' defined depending on a capacitance ratio of the two capacitors. This voltage is outputted through the operational amplifier 19 and the buffer 20.
When a high level control signal S2 is supplied to the circuit at a timing point T2, the analog switch 16 is switched on so that the signal Y is applied to the capacitor 17. Hence, the capacitor 17 is charged with the signal Y. Thereafter, when the signal S2 falls to the low level and the analog switch 16 is switched off, the capacitor 17 holds the voltage D2 of the signal Y immediately before the fall. Then, the high level control signal R is supplied to the circuit. In response to the high level signal R, the transistors 21, 22 are switched on so that the output of the buffer 20 becomes the ground level and the capacitor 15 is discharged. When the control signal S4 rises to the high level, the analog switch 18 is switched on so that the charges of the capacitor 17 are moved to the capacitor 15. As a result, the voltage at the terminals of the capacitors 17 and 15 is made to be a value D2' defined depending on a capacitance ratio of the two capacitors. This voltage is outputted through the operational amplifier 19 and the buffer 20. By alternately switching on the analog switches 12 and 16, the voltages D3, D4, . . . of the signal Y are sampled and held in the capacitors 13, 17, and 15. Then, the voltages D3', D4', . . . corresponding to the voltages D3, D4, . . . are outputted from the circuit.
The known sample and hold circuit arranged as described above serves to move part of the charges of the capacitors 13, 17 to the capacitor 15. Therefore, the voltages (D1, D2, . . .) of the sampled signal Y are attenuated. For example, assuming that the charges of the capacitor 13 is denoted as Q0 and the electrostatic capacitance of the capacitor 13 is denoted as C1, the voltage V0 at the terminal of the capacitor 13 is defined by the following expression. EQU V0=Q0/C1
When the analog switch 14 is switched on while keeping the charges of the capacitor 13 at Q0, since the capacitors 13 and 15 are connected in parallel, the voltage V1 at the both terminals of the capacitors is defined by the following expression. EQU V1=Q0/(C1+C2)
wherein C2 denotes an electrostatic capacitance of the capacitor 15. As is apparent from the above expression, V1&lt;V0 is given. Hence, the voltage inputted to the operational amplifier is lower than the voltage held in the capacitor 13. This holds for the capacitor 17. That is to say, when the analog switch 18 is switched on and the capacitor 15 becomes connected in parallel to the capacitor 17, the voltaage drops. Hence, the voltage inputted to the operational amplifier is lower than the voltage held in the capacitor 17.